This invention generally relates to polishing slurries and more particularly to polishing slurries with a bimodal mean particle size useful for chemical mechanical polishing (CMP) of semiconductor wafers including copper metal interconnects formed in low-k dielectric material.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers may be accomplished using various fabrication techniques including oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
Planarization, for example, is an increasingly important in semiconductor manufacturing technology. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe restraints on the degree of planarity of a semiconductor wafer processing surface. Excessive degrees of process surface nonplanarity will affect the quality of several semiconductor process including, for example, in a photolithographic process, the positioning the image plane of the process surface within an increasingly limited depth of focus window to achieve high resolution semiconductor feature patterns.
One planarization process is chemical mechanical polishing (CMP). CMP is increasingly being used for planarizing dielectrics and other layers, including applications with increasingly stringent critical dimension semiconductor fabrication processes. CMP planarization is typically used several different times in the manufacture of a multi-layer semiconductor device. For example, CMP is used as one of the processes in preparing a layered device structure in a multi-layer device for subsequent processing. CMP is used to remove excess metal after filling conductive metal interconnects such as vias and trench lines with metal to electrically interconnect the several layers and areas that make up a multi-layer semiconductor device.
In a typical process for forming conductive interconnections in a multi-layer semiconductor device a damascene process is used to form vias and trench lines for interconnecting different layers and areas of the multilayer device. Vias (e.g., V1, V2 etc. lines) are generally used for vertically electrically interconnecting semiconductor device layers and trench lines (e.g., M1, M2, etc. lines) are used for electrically interconnecting semiconductor device areas within a layer. Vias and trench lines are typically formed as part of a damascene process. Although there are several different methods for forming damascene structures, one typical method generally involves patterning and etching a semiconductor feature, for example a via opening within an insulating dielectric layer to make contact with a conductive area within an underlying layer of the multilayer device. The via opening (plug) may then be filled with for example, copper to form a via (plug) followed by a CMP step to remove excess metal deposited on the insulating dielectric layer surface and to planarized the surface for a subsequent processing step. A second insulating dielectric layer is then deposited followed by patterning and etching the second insulating dielectric layer to form a trench opening situated over the via. The trench opening is then filled with a metal, for example, copper, to form trench lines (intra-layer horizontal metal interconnections). A second CMP step is then carried out similar to the first CMP step to remove excess metal and to planarize the process wafer surface in preparation for further processing.
CMP is widely accepted as the preferred process for many planarization processes including planarizing copper filled trench lines. CMP is the method of choice particularly for smaller device fabrication technologies including dimensions of less than about 0.27 micron. CMP generally includes placing a process surface of the wafer in contact against a flat polishing surface, and moving the wafer and the polishing surface relative to one another. The polishing action is typically aided by a slurry which includes for example, small abrasive particles such as colloidal silica (SiO2) or alumina (Al2O3) that abrasively act to remove a portion of the process surface. Additionally, the slurry may additionally include chemicals that react with the process surface to assist in removing a portion of the surface material, the slurry typically being separately introduced between the wafer surface and the polishing pad. During the polishing or planarization process, the wafer is typically pressed against a rotating polishing pad. In addition, the wafer may also rotate and oscillate back and forth over the surface of the polishing pad to improve polishing effectiveness.
Typically CMP polishing slurries contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium. There are various mechanisms disclosed in the prior art by which metal surfaces can be polished with slurries. The metal surface may be polished using a slurry where a surface film is not formed causing the process to proceed by mechanical removal of metal particles. In using this method, the chemical dissolution rate should be slow in order to avoid wet etching. A more preferred mechanism is, however, one where a thin abradable layer is continuously formed by reaction between the metal surface and one or more components in the slurry such as a complexing agent and/or a film forming layer. The thin abradable layer is then removed in a controlled manner by mechanical action. Once the mechanical polishing process has stopped a thin passive film remains on the surface and controls the wet etching process. Controlling the chemical mechanical polishing process is much easier when a CMP slurry polishes using this mechanism.
There are also several different types of slurries used in the CMP process. The most common abrasives used are silica (SiO2), alumina (Al2O3), ceria (CeO2), titania (TiO2), and zirconia (ZrO2). The abrasives are typically formed using two different methods that result in fumed and colloidal abrasives. Fumed abrasives include agglomerated particles that are larger in size than the dispersed, discrete particles of colloidal abrasives. For the same solids concentration, the removal rate using a fumed abrasive is higher than that using a colloidal abrasive due to sharp edged particle features and a broader particle size distribution in fumed abrasives. For the same reasons, the defect density using a fumed abrasive also tends to be higher.
To minimize defect formation, the colloidal abrasives having a more uniform particle size distribution are preferred. However, to achieve the same material removal rate as using a fumed abrasive, the solids concentration of a colloidal slurry must be almost three times higher. The higher required solids concentration undesirably increases the cost of the slurry.
One particular problem with the prior art methods of CMP involve the unique problems inherent in the increasing use of low-k(dielectric constant) materials as an inter-layer dielectric (ILD) together with copper filled vias and copper interconnect lines (trench lines). The low-k insulating dielectrics generally tend to be highly porous in an effort to lower dielectric constants lower than about 3.0 thereby lowering capacitive effects in the ILD. Lower capacitances are required to reduce signal delay times as feature sizes decrease. Additionally, copper has become the conductor of choice for metal interconnects as device sizes decrease primarily due to low resistivity. Several different materials have been proposed for use as low-k materials including porous inorganic and organic material. Exemplary inorganic materials include, for example, carbon doped silicon dioxide and fluorinated silicon dioxide while some of the organic materials include, for example, Poly(arylene) Ethers, Poly (benzocyclobutenes) and perfluorocyclobutanes (BCB and PFCB), Polytetrofluoroethylene (PTFE), Paralyne-N, Paralyne-F, and Siloxanes.
Some of the unique problems presented by the use of copper together with low-k dielectric materials include for example, poor adhesion between the copper metal and the low-k material, causing peeling to occur upon subjecting the multilayer device to the stresses caused by CMP. Other defects associated with CMP of copper together with low-k materials have included dishing in relatively wide copper areas such as bonding pads and erosion in relatively long and narrow metal filled areas such as copper metal interconnects. Additional CMP defects include unacceptable scratch size, and leaving copper residue on the CMP target surface leading to electrical opens and shorts.
For example, referring to FIG. 1A, a cross sectional side view representation of a portion of a semiconductor waver is shown showing metal interconnect lines (trench lines) e.g., 12A, 12B, 12C filled with copper by forming copper layer 16 over the trench line openings after forming barrier layers e.g., 14, for example tantalum nitride (TaN) within the trench line openings anisotropically etched into a dielectric material for example carbon doped oxide. One of the trench lines, e.g., 12B is shown formed slightly lower resulting in a recessed copper area 16A. IN a typical CMP process, a compressive force directionally indicated by arrow 22 is applied polishing pad 18 which transfers the applied compressive force to the surface of copper layer 16 through a polishing slurring including abrasive particles e.g., 20. As conceptually represented in FIG. 1B, the upon polishing the copper layer 16 to achieve planarity, the polishing force cannot effectively be applied to obtain polishing action in recessed area 16A if the abrasive particles e.g., 20, have a mean diameter smaller than the recessed dimension. As a result, copper residue in recessed area 16A is left on the semiconductor wafer surface causing, for example, an electrical short.
Further, the lower strength of the low-k materials has led to increased vulnerability of copper/low-k systems to CMP induced defects caused by slurries using abrasives with relatively high hardness such as fumed alumina and silica. On the other hand, slurries with colloidal particles including alumina and silica require excessively long polishing times unacceptably reducing wafer throughput. As such, it has been difficult to develop CMP methods including abrasives slurries that can accomplish both requirements of high material removal rate while minimizing the introduction of defects at the semiconductor wafer surface.
For example, using a fumed alumina (Al2O3) slurry system dishing over about a 120 micron by about 120 micron square area results in an out-of-planarity dimension of greater than about 2500 Angstroms while a silica (Si2O3) system has dishing over the same area of less than about 1000 Angstroms. The same results hold for erosion over a square area of about 300 by about 300 microns. The Cu removal rate using a fumed alumina (A1203) slurry is typically about 4500 to about 9000 Angstroms/min, while a fumed silica slurry typically has a removal rate of about 5000 Angstroms/min. Both the alumina and silica slurry systems typically have some associated peeling of low dielectric layers associated with copper interconnect lines.
Therefore, there is a need in the semiconductor art to develop a slurry for CMP that is able to accomplish both the goals of achieving acceptable material removal rates while minimizing CMP induced defects.
It is therefore an object of the invention to provide a slurry for CMP use in semiconductor wafer polishing that is able to accomplish both the goals of achieving acceptable material removal rates while minimizing CMP induced defects and additionally overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a bimodal slurry system for a chemical mechanical polishing process
In a first embodiment of the present invention, the bimodal slurry system includes a dispersion comprising a plurality of first particles and a plurality of at least one type of second particles said first particles having a mean particle diameter larger by at least a factor of 3 than a mean particle diameter of the at least one type of second particles said first particles further being compressible.
In related embodiments, the plurality of first particles has a mean particle diameter of from about 100 nanometers to about 300 nanometers. Further, the plurality of at least one type of second particles has a mean particle diameter from about 10 nanometers to about 50 nanometers.
In another embodiment, the first plurality of particles includes a material having a Young""s Modulus of from about 10 to about 200 kPa over a temperature range of about 25 degrees Centigrade to about 80 degrees Centigrade.
In yet another embodiment, a portion of the plurality of at least one type of second particles is disposed around the periphery of at least a portion of the plurality of first particles.
In another embodiment, the plurality of at least one type of second particles includes at least one of a metal oxide, a carbide, and a nitride. Further, the metal oxide is produced by a fuming process.
In another related embodiment, the plurality of at least one type of second particles includes at least one of alumina, titania, zirconia, germania, silica, and ceria.
In another embodiment the first particles are formed of a polymer containing material. Further, the polymer containing material includes an elastomer. Further yet, the elastomer is a polyurethane containing material. Yet further, the polyurethane containing material has a hardness of about 70D to about 95D according to an elastomer durometer hardness test.
In another embodiment, the plurality of first particles has a relatively lower hardness compared to the plurality of at least one type of second particles according to an equivalent Rockwell hardness.
In a related embodiment, the plurality of first particles is formed of a porous inorganic material having an interconnecting porosity from about 20 to about 80 percent.
In other related embodiments, the bimodal slurry further includes at least one of an oxidizer, a complexing agent, and an organic amino compound. Further, the bimodal slurry includes a total solids content of about 0.1 percent to about 10 percent. Further the ratio of the plurality of first particles to the plurality of at least one type of second particles is from about 5 percent to about 60 percent.
In another embodiment, the plurality of first particles and the plurality of at least one type of second particles include at least one of agglomerated primary particles and dispersed primary particles.
In a related embodiment, the plurality of first particles includes substantially dispersed primary particles and the plurality of at least one type of second particles includes agglomerated primary particles. In another related embodiment, the plurality of the at least one type of second particles are substantially dispersed primary particles.